(1). Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory device, and more particularly, to a method of forming a cylindrical capacitor in the fabrication of a dynamic random access memory device.
(2). Description of the Prior Art
Dynamic random access memory (DRAM) devices are widely used in the art. In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering of source/drain ratio and undesirable signal problems. In order to achieve the desired higher level of integration, the technology must keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked cylindrical capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. In U.S. Pat. No. 5,346,844 to Cho et al, there is described a method of forming a cylindrical capacitor using a poly plug process. FIGS. 1 through 4 illustrate such a conventional poly plug process.
Referring to FIG. 1, there is illustrated a partially completed DRAM integrated circuit device in which is shown a semiconductor substrate 10. Semiconductor device structures, such as gate electrodes, not shown, are fabricated in and on the semiconductor substrate and covered with a thick oxide layer 15. A layer 17 of silicon nitride is deposited over the oxide layer. An opening is etched through the silicon nitride and oxide layers and filled with polysilicon which is etched back to form the poly plug 19. This opening is typically 0.3 to 0.35 microns wide. If the opening is too deep, it may be difficult to completely fill the opening. If the polysilicon is not etched back enough, polysilicon residue 21 may be left on the surface of the silicon nitride layer.
Referring now to FIG. 2, a second oxide layer 23 is deposited over the silicon nitride layer and the poly plug. A second photoresist mask is used to provide an opening having a width of between about 0.5 to 0.6 microns. The opening is etched through the second oxide layer 23 to the poly plug 19. A second polysilicon layer 27 is conformally deposited within the opening, as shown in FIG. 3, to form the bottom plate electrode of the capacitor.
If there is misalignment of the second photoresist mask 25, as shown in FIG. 4, the second polysilicon layer 27 does not completely cover the poly plug 19. Next, the polysilicon layer 27 is patterned, and the oxide layer 23 is stripped. If there is misalignment, as in FIG. 4, the portion of the poly plug 33 not covered by the polysilicon layer 27 will be exposed. This is a weak point. The oxide etch, such as buffered oxide etch (BOE) will etch through the weak point 33 and cause peeling of the silicon nitride layer 17 at that point.
Metal plug processes are discussed in ULSI Technology, by Chang and Sze, McGraw-Hill, New York, N.Y., c. 1996, pp. 444-445. U.S. Pat. Nos. 5,409,855 to Jun and 5,554,557 to Koh teach methods of forming cylindrical capacitors without using a poly plug process, but do not address the misalignment and deep recess problems.